In the related art, a technology for providing a pad for wire bonding and probing in a semiconductor substrate placed on a lower side to prevent cracks from occurring when two semiconductor substrates are to be joined together and electrically connected using through holes is known (for example, refer to Patent Literature 1). Here, the semiconductor substrate placed on the lower side is a semiconductor substrate placed on the opposite side to the side on which wire bonding and probing are performed (an upper side).
The pad for wire bonding and probing is provided on the semiconductor substrate on the lower side because if the pad is provided on the semiconductor substrate on the upper side, a load exerted on the semiconductor substrate at the time of wire bonding and probing is concentrated on an insulating film portion below the pad, which causes cracking.
In addition, a technology in which, when electrical connection of upper and lower wafers (semiconductor substrates) is realized by bonding Cu electrodes and insulating films at the same time, a Cu dummy pad is provided in the bonding surface of the wafers for planarizing the Cu portion or the insulating films has also been proposed (for example, refer to Patent Literature 2).